1. Field of the Invention
The present invention relates to a digital signal processor and particularly to a digital signal processor improved to perform digital signal processing efficiently.
2. Description of the Prior Art
A digital signal processor is a microprocessor dedicated to digital signal processing, developed for the purpose of rapidly performing arithmetic operations of multiplication and addition frequently required for digital signal processing.
FIG. 1 is a schematic block diagram showing an example of a conventional digital signal processor disclosed for example in "A Single-Chip Digital Signal Processor for Voiceband Applications" by Y. Kawakami et al., 1980 IEEE International Solid-State Circuits Conference, pp. 40-41. Referring to FIG. 1, the digital signal processor comprises, as in an ordinary microcomputer, a memory portion 1, a control portion 2, an arithmetic operation portion 3 and a data bus 4. The memory portion 1 comprises a random access memory (refcrred to hereinafter as a RAM) 11 and a read-only memory (referred to hereinafter as a ROM) 12. Data to be processed in the arithmetic operation portion 3 and data necessary for the processing are stored in the RAM 11 and the ROM 12. Non-fixed data is stored in the RAM 11 and fixed data (for example, constant data, etc. for multiplication) is stored in the ROM 12. The RAM 11 and the ROM 12 are connected with the data bus 4.
The control portion 2 comprises an instruction ROM 21, a program counter 22, an instruction register 23 and an instruction decoder 24. Program data is stored in the instruction ROM 21. The program counter 22 reads out successively the program data from the instruction ROM 21 in synchronism with a basic clock (not shown) of the digital signal processor. The instruction register 23 stores temporarily the program data read out from the instruction ROM 21. An output from the instruction register 23 is supplied to the instruction decoder 24. Part of bit output from the instruction register 23 is supplied to the data bus 4. The instruction decoder 24 decodes the program data received from the instruction register 23 and provides various control signals. Those control signals are supplied to the memory portion 1, the control portion 2, the arithmetic operation portion 3, etc. so as to control operation of the internal circuits of those components.
The arithmetic operation portion 3 comprises a multiplier 31, an arithmetic and logic unit (referred to hereinafter as an ALU) 32 and an accumulator 33. Inputs of the multiplier 31 are connected with the data bus 4. One of the inputs of the multiplier 31 is connected directly with the RAM 11 and the other input thereof is connected directly with the ROM 12. An input of the ALU 32 is connected with the data bus 4 and is connected directly with the multiplier 31. The other input of the ALU 32 receives an output from the accumulator 33. An output from the ALU 32 is supplied to the accumulator 33. The accumulator 33 is connected with the data bus 4.
In the above described construction, the multiplier 31 multiplies a value read out from the RAM 11 by a constant read out from the ROM 12 and supplies the result of multiplication to the ALU 32. The ALU 32 adds the result of multiplication by the multiplier 31 to the accumulating total value of the results of multiplication obtained so far and stored in the accumulator 33 so that the result of addition is stored in the accumulator 33. The accumulating value stored in the accumulator 33 is provided through the data bus 4.
Thus, since the digital signal processor comprises the multiplier 31 as a hardware circuit dedicated to multiplication processing, multiplication processing can be performed at a higher speed as compared with the case of performing multiplication as repetition of addition operation in the ALU 32 as in a conventional microcomputer. In addition, since the multiplier 31 is connected directly with the RAM 11 and the ROM 12, data can be set in the multiplier 31 by one instruction. Furthermore, since the multiplier 31 is connected directly with the ALU 32, a result of multip1ication can be set in the ALU 32 by one instruction. Thus, data paths for arithmetic operations of multiplication and addition are provided separately from the data bus 4 and accordingly arithmetic operations of multiplication and addition can be performed simultaneously with transfer of data and processing for arithmetic operations of multiplication and addition can be performed at high speed.
However, in such a digital signal processor as described above, the calculating speed in the multiplier 31 is slowest compared with the processing speed in other circuits. As a result, in such a conventional digital signal processor, the throughput rate is usually determined dependent on the calculating speed of the multiplier 31 and further improvement in the throughput rate cannot be made.